module keni_cnt10(
input clk,
input rst,
output reg[3:0]q
);
integer state = 0;
always@(posedge clk) begin
	if (rst) begin
		q = 0;
	end
	else begin
		if (q == 9)
			state = 1;
		else if (q == 0)
			state = 0;
		if (state == 1)
			q = q - 1;
		else
			q = q + 1;
	end
end

endmodule
